Ivan Stankovic wrote:
On Mon, Mar 15, 2010 at 04:47:05PM -0500, John Griessen wrote:Al wants more info than you get with SPICE netlist formats. So Verilog-ams level of function is possible.While we're at it, was there a consensus on using verilog-ams as the format of choice for Al's translation system?
Consensus? Not yet. Al does ask for two way translatable formats, so including enough info to recreate a schematic is implied, but not how exactly appearance matching it will be. I'm thinking of graphic elements as only the generic rectangular boxes at first, then by way of text attributes, add more later. the detailed info to recreate schematic appearance is not needed for effective translation purposes, just connectivity. A reasonable goal is to capture data that assists in putting back a schematic as it was, but not "doing the layout" part of a schematic. A big assist would be to keep any unique identifiers from schematic symbols until a symbol is changed for simulation purposes. Then one could relate the simulation netlist points to the original schematic points for cross probing, even when the sim netlist is a subset or different in part from the original. Then you could do a process of back annotating, deleting schematic symbols not found in the sim netlist, and saving the modified schematic as an aid to simulation displaying. With a small amount of "symbol layout" time, your new schematic for cross-probing purpose would be a one-to-one match with the simulation. Al asked for a format for electric/electronic netlists that can include any simulator's or schematic/netlist capture program's circuit information. John -- Ecosensory Austin TX _______________________________________________ geda-user mailing list geda-user@xxxxxxxxxxxxxx http://www.seul.org/cgi-bin/mailman/listinfo/geda-user