Re: gEDA-user: Some kind of library manager and hierarchical netlisting

[John Doty <jpd@xxxxxxxxx>]

On Nov 19, 2008, at 5:17 PM, r wrote:

> Agreed. I didn't mean gnetlist doesn't work with hierarchical designs
> at all - it just didn't produce any useful results last time I tried
> it.

You haven't clearly stated what your problem was. I've done both  
hierarchical VLSI designs (SPICE style: generate a hierarchical  
netlist with a Makefile and let the downstream tools flatten it), and  
circuit boards (use source= and let gnetlist do the flattening).  
Works great for me. Nobody can fix a problem you can't clearly  
articulate.

> I've looked into the scheme code but I couldn't find any obvious
> errors. This single error broke my workflow, I think it is important
> enough to inform others that they should not rely on this particular
> feature.

What error?

John Doty              Noqsi Aerospace, Ltd.
http://www.noqsi.com/
jpd@xxxxxxxxx




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