Re: gEDA-user: Some kind of library manager and hierarchical netlisting

[r <nbs.public@xxxxxxxxx>]

On Wed, Nov 19, 2008 at 2:49 PM, Peter Clifton <pcjc2@xxxxxxxxx> wrote:
> On Wed, 2008-11-19 at 06:04 -0800, Steve Meier wrote:
>> Peter,
>>
>> I believe that gnetlist takes in a hierarchical series of schematics and
>> flattens the schematics into a flat netlist that may then be exported
>> into a number of flat formats. In other words the net has been flattened
>> before reaching the backend. Hierarchical information is retained in
>> reference designators and in net names.
>
> You are, of course, correct. IIRC, there were a few workarounds for the
> VHDL / spice backends, where individual pieces were netlisted
> separately. Its been a while since I looked, and certainly those cases
> are non-optimal, even if it is possible to retain hierarchy.

Agreed. I didn't mean gnetlist doesn't work with hierarchical designs
at all - it just didn't produce any useful results last time I tried
it. I've looked into the scheme code but I couldn't find any obvious
errors. This single error broke my workflow, I think it is important
enough to inform others that they should not rely on this particular
feature.

> There are possibly some workarounds available, such as net-listing
> individual pieces separately, but we (gEDA) really ought to work on
> doing better.

IMHO netlister front-end should be included in libgeda (for example as
an iterator returning all the pins, nets, primitives, subcells in the
design). It is a single best place to locate all the logic translating
graphical shapes/file format into a circuit. Otherwise every tool has
to reimplement this logic from scratch based on conventions. Such a
"circuit information" would also be very useful for gschem itself - it
would be possible, for example, to perform some sanity checks (pin
mismatches, shorts, unconnected nets etc) or assist the designer
(highlighting nets).

Best regards,

-r.


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