Re: gEDA-user: next PCB release - 1.99za vs 4.0

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Fri, 2010-09-10 at 11:03 -0700, Andrew Poelstra wrote:

> It's a PITA to find and read the geda-dev archives, and given the relatively
> low volume, I don't usually bother. So I missed your comments.

If you're developing, ask Ales to get you signed up to geda-dev. As you
say, it is pretty low volume.

> Having said that, I'd do you one step further, and move /all/ the layers into
> their own list structure. Each layer would have flags set to indicate if it
> was a copper, silk, keepout or virtual (ie, ratsnest) layer. They would also
> be tagged as being always on top or always on bottom, in the case of silk
> layers that we don't want ending up inside the board.

Yes, indeed.. magic silk (and other) layers should probably go and die.

It was sorely tempting to do that earlier. For now, I've pushed a patch
which makes it a little clearer what the intent is when iterating over
layers / groups. I wanted to come up with a better name that
"max_copper_layers", but I guess that can change when we actually put
some non-copper layers in place. "max_normal_layers"?

(Or just "max_layers" once again, when we've made all layers equal).
Perhaps it would be good to use a new name though.. to avoid silent
breakage on old plugins which assume the old semantics though.

Whatever we do, it is still useful to be able to designate component /
solder side groups (or have some means to define physical stack-up) so
that pads can be rendered on the right layers ;)

> > Point me some examples and I'll probably agree, but I can't think of any
> > immediately.
> 
> Well, the fact there are exactly two silk layers, both selected in the same
> way (depending on which side of the board is being viewed), and a ratsnest
> layer, all of which require switch blocks throughout the layer-selector GUI
> code. Also, there are weird variables like SilkActive and RatsActive that
> implicitly depend on each other, and the layer array.

Ok, I've got you... and you are correct ;)

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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