Re: gEDA-user: Heavy Symbols and such

[Steve Meier <smeier@xxxxxxxxxxxxxxxxxxx>]

I wish it would be that easy.

The problem is that the number of io pins that needed for some section
of a design is dependent upon how you group board functions together and
the number / type of pin on the other devices.

But If I could have a program where I could say please mr wizard break
that nasty fpga up into the following symbols and here are the
rquirements for each symbol.

Logic Family, number of differential i/o pins, do the clocks need to be
from the same pll, do we need to make use of slight delays from i/o pin
to i/o pin etc etc and every year the list gets longer.

Yes an autogeneration of symbols would be best and reduce over all
headackes. is that pin really on that i/o bank and did i really hook the
reference voltage up to the right voltage source. The level of this
detail can be hair pulling and then you are frought with fear..... waht
if I blew it and I mixed my power, ground pins costing a turn of the
board and the disposal of a lot of expensive parts.

But one of the nice things about fpga's is that when you flip the two
differential pins... you just put an inverter into the logic and un-flip
them.

Steve Meier

John Griessen wrote:
> DJ Delorie wrote:
>
>   
>>> And another one: does gschem fully grasp the "2-in" concept with
>>> swapable pins ?
>>>       
>> Not directly.  I've built parts with "slots" for various input pin
>> permutations.
>>
>>     
>>> All gschem and pcb have in common is the refdes, pin info and
>>> connectivity.
>>>       
>> Yup.  But they, as tools, wouldn't be useful to us if that was all
>> they *could* deal with.
>>     
>
>
> So, commanding slot changes could be all that is needed for pin swapping.
> For a FPGA, there wold be so many slots, one might do best just running a
> search for the other slot with the same two pin numbers in it.  Creating
> a working FPGA slotted symbol would be a job for a program, not a person...
>
> Steve?
>
> John Griessen
>   



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