Re: gEDA-user: Insufficient clearance of pad inside polygon

[DJ Delorie <dj@xxxxxxxxxxx>]

> Ok, one of the drc tests, apparently, is to test if a land pattern
> conforms to the design rules (e.g. silk screen thickness) why doesn't
> the drc run every time a land pattern is dropped into a layout? Is it
> not better to be proactive then reactive?

I hope by the time you've got an element in your library it's passed
some sort of QA.  However, my previous comment fits here too - the DRC
parameters may change over time.  I can see a need to switch to more
restrictive DRCs for cost savings, or globally "ease off" if a looser
DRC is selected.  The first needs the fix-on-the-fly solution, the
second needs the global change option.  You might not even know the
DRC parameters until late in the design.

For silkscreen on dense boards, line thickness might not even be a
design consideration.  You'd just set it to as thin as the fab house
allows just before you send it out.

Note that PCB does have restrictions on where you can put vias; it
won't let them overlap for example.  There are *some* drc-on-the-fly
features built in, it's just not 100% coverage.

From personal experience, I was building my smd adapter and set the
line thickness equal to half the pad spacing - so that the lines and
the gaps were the same width, hoping to avoid both narrow traces
(broken traces) or narrow spacing (shorts).  Because of the way I did
the board, the traces came out wider than expected, so I'd have to go
back and adjust everything and try again.  So the DRC parameters
change with experience.