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Re: CRC (was Re: [f-cpu] F-CPU architecture...)

the most usual CRC32 implementation is the Ethernet one, it is used almost everywhere.
Now i wonder how it could handle more than 1 or 2 bytes per cycle (the memory paths
are certainly faster than that).

Ethernet CRC common but there are few other common ones also. Parallel implementations are quite fast, 64bit at a time ethernet crc is about 6 level deep xor-network that contains about 1500 2-input xor gates (rough estimates from memory). 6 levels of xor gates is about 6*70ps at 0.13u, add some wire delay and you still get quite respectable speed :) And CRC calculation can be pipelined if needed, but that is little more difficult. The single cycle xor-network is quite trivial and well known in the literature.

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