Re: gEDA-user: terminators

[Gabriel Paubert <paubert@xxxxxxx>]

On Mon, Apr 06, 2009 at 10:41:57PM -0400, DJ Delorie wrote:
> 
> > That could work too. But, honestly, from what I see on your board
> > what's the problem besides the stubs?
> 
> If I knew that answer, I wouldn't need to ask all these questions.
> 
> > Oh, and make sure to set the constraints on your fpga so the timing is 
> > right-on.
> 
> Yet another thing to learn how to do...

Well, in most cases this reduces to forcing the synthesis/mapping
tools to use the IOB flip-flops (in VHDL it becomes something
like "attribute IOB of <whatever>:signal is true;" in the top
level file). Otherwise difference in routing delays between internal 
flip-flops and IOB is much larger than an inch of trace length 
difference on the board. 

Yesterday the automatic placer did something extremely stupid on 
a test of mine and I had 2 nS of routing only beween an IOB and a 
FF. The simulated annealing or however it's called sometimes
produces awful placements (and I had less than 1% of the chip
used, an XC3S200A-FT256). Floorplanning can help a lot
in these cases.

	Gabriel


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