DJ Delorie wrote:
"bus pin" confuses me. Is there another name for what you are thinking?It's a symbolic pin that means multiple physical pins. It can look the same or look different, doesn't matter to me, but I figured a bus pin would be thicker, and could connect directly to a bus, instead of having to make a net mean both a single signal and a group of signals.
Thanks. The chip design tools don't worry with making busses look any different unless added by the user just for looks. For them, the different label does it all. But they done' have that additional constraint of a package. I guess bus pin is workable terminology. Bus port for a name might cause less head aching. Dietmar Schmunkamp wrote: >> No reason you couldn't attach some random attribute to the bus that's >> just to give it a mnemonic name :-) > > DJ, > > in general I don't like having 2 names for the same net, Maybe I'm > biased with my experience of vhdl synthesis, normally the name that you > don't expect survives synthesis and the other one gets lost (and that > even may vary between two releases of the same tool). So having only one > name has advantages. Same in chip design. Names get really long. No one complains because verification is the ultimate in chips. 2nd trips through the fab to get working silicon are deadly to company financial health. John _______________________________________________ geda-user mailing list geda-user@xxxxxxxxxxxxxx http://www.seul.org/cgi-bin/mailman/listinfo/geda-user