DJ Delorie wrote:
You can refer to the nets within the bus when you pull them out for a connection: A[0:15],D[0:7],RD,WR,EN - all the nets A[0:1],RD,EN - some of the nets A15,D[0:7],WR,EN - some of the nets but we could also give the *grouping* a name, like "CONTROL_BUS".
That's what Dietmar is warning against... one way refers to A[0:15],D[0:7],RD,WR,EN as "CONTROL_BUS" and then it gets confused later as just meaning A[0:1],RD,EN. But if we kept it from being used for connections and just as a shorthand for schematics readability, I'm all for that. When you get big busses and big FPGA chips and more than a few hundred pins or pads, I think schematics break down in usability anyway and verilog netlists are the thing to do. -- John _______________________________________________ geda-user mailing list geda-user@xxxxxxxxxxxxxx http://www.seul.org/cgi-bin/mailman/listinfo/geda-user