Re: gEDA-user: Out and In symbols in gschem & getting net names to come out in PCB

[Stephan Boettcher <boettcher@xxxxxxxxxxxxxxxxxx>]

Kai-Martin Knaak <kmk@xxxxxxxxxxxx> writes:

> Colin D Bennett wrote:
>
>> +1000 for a patch to make I/O pin symbols visually clean without
>> requiring maintaining duplicate attributes as at present.
>
> While I am all in favor to get rid of the ":1", this is how I currently 
> deal with net names:
>
> * For nets that jump inside a sheet I attach an attribute to a short
> net line stub. I copy/paste this stub to where ever the net should go.
>
> * For nets that enter the sheet from a higher level of hierarchy, I use 
> in.sym and out.sym and set the refdes to the desired net name (without a 
> ":1" appendix).

dito, plus:

* For power/ground nets I create a symbol with a label and hidden net=
  attribute.

* For small projects I use the generic power symbol and live with the
  ugly :1 at the end of the netname, when the standard Vcc, Vdd, Vee, Vss,
  and GND symbols are not sufficient.

-- 
Stephan


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