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Re: gEDA-user: the uber-scope (was: wishful UI)

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Subject: Re: gEDA-user: the uber-scope (was: wishful UI)
From: Peter Clifton <pcjc2@xxxxxxxxx>
Date: Fri, 20 Aug 2010 14:39:56 +0100
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On Fri, 2010-08-20 at 12:37 +0200, Armin Faltl wrote:
> VHDL - thats specs for a silicon compiler, right? - so you are using 
> ASICs in
> "hobby"-project?

VHDL / Verilog is also used for developing with FPGAs.

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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Follow-Ups:
- Re: gEDA-user: the uber-scope (was: wishful UI)
  - From: Oliver King-Smith

References:
- Re: gEDA-user: wishful UI
  - From: Andrew Poelstra
- Re: gEDA-user: wishful UI
  - From: Stefan Salewski
- Re: gEDA-user: wishful UI
  - From: Stefan Salewski
- Re: gEDA-user: wishful UI
  - From: Andrew Poelstra
- Re: gEDA-user: wishful UI
  - From: Stefan Salewski
- Re: gEDA-user: wishful UI
  - From: Andrew Poelstra
- Re: gEDA-user: wishful UI
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- Re: gEDA-user: wishful UI
  - From: Armin Faltl
- Re: gEDA-user: wishful UI
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- Re: gEDA-user: wishful UI
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- Re: gEDA-user: wishful UI
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- Re: gEDA-user: wishful UI
  - From: Stefan Salewski
- Re: gEDA-user: wishful UI
  - From: Rick Collins
- Re: gEDA-user: wishful UI
  - From: Stefan Salewski
- Re: gEDA-user: the uber-scope (was: wishful UI)
  - From: Armin Faltl

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