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Re: gEDA-user: General Layers questions
On Mar 19, 2011, at 12:33 PM, John Doty <jpd@xxxxxxxxx> wrote:
>
> On Mar 19, 2011, at 1:20 PM, Steven Michalske wrote:
>
>> This is what bothers me about a hole layer, un plated vs plated, the holes do not define electrical contact, the plating does.
>>
>> Or, rivits, or the soldered wires on hand assembled multilayer boards.
>>
>> Well with silver ink circuit printing. The hole in the sprayed on insulators does define the connectivity....
>>
>
> This demonstrates a flaw in the "hole layer" concept. It doesn't actually capture the geometry. But if the layers are physical, the objects in them might have different properties. So a plated-through hole is geometrically a place in a layer that is mostly insulator, but has a conductive annulus at a particular place.
>
Oh my! You can draw The plating on the insulator layer. Thus making the plating a real object of conductor.... This is more 3d cad leaking through.
That would mean that drawing on a insulator/separator would define some material to replace the seperator with, and they would need properties. Plated through hole, conductive epoxy filled, thermal epoxy filled.
The drawn shapes would need properties....
The exporter would see a hole and it's anulis and drill a hole the size of the anulis or hole based on a flag in the exporter about the fab shop's preference on finished or drill sizes.
Edge plating would be a line drawn at the egge of the board that moved in the outline of the pcb by the plating thickness.
A plating tool could be made to draw the required shapes on each layer through the board. Like the copper trace on the copper layers to plate to and the plating on the insulator.
> John Doty Noqsi Aerospace, Ltd.
> http://www.noqsi.com/
> jpd@xxxxxxxxx
>
>
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>
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