Re: gEDA-user: next PCB release - 1.99za vs 4.0

[Peter Clifton <pcjc2@xxxxxxxxx>]

On Fri, 2010-09-10 at 15:01 -0400, DJ Delorie wrote:
> > Whatever we do, it is still useful to be able to designate component
> > / solder side groups (or have some means to define physical
> > stack-up) so that pads can be rendered on the right layers ;)
> 
> I figure we need each layer to specify:
> 
> * type (copper, silk, mask, anti-copper, keepout, etc)
                                ___^___

Just how useful is anti-copper?

Is it mitigated by allowing holes in polygons?

I do have some code (not sure what state it is in) which implements
anti-polygons within a given layer. It was my first stab at figuring out
a way to allow user-specified holes in polygons. I have been rebasing
that branch against current changes "just in case" it would ever be of
any use, but I had basically consigned as an idea that went nowhere.

>   - probably a set of values: base type plus flags for "anti" etc
>   - maybe a sequence number for layering, like anti-silk over silk rectangles, etc.

Presumably anti- layers would have be be composited into a single output
layer by for various exporters?

-- 
Peter Clifton

Electrical Engineering Division,
Engineering Department,
University of Cambridge,
9, JJ Thomson Avenue,
Cambridge
CB3 0FA

Tel: +44 (0)7729 980173 - (No signal in the lab!)
Tel: +44 (0)1223 748328 - (Shared lab phone, ask for me)



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